A CMOS imager circuit includes a focal plane array of pixels, each of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that includes at least an output field effect transistor and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
FIG. 1 illustrates a conventional CMOS imager 100 having a pixel array 102 connected to column sample and hold (S/H) circuitry 136. The pixel array 102 comprises a plurality of pixels 110 arranged in a predetermined number of rows and columns. The illustrated pixel 110 shown is a four transistor pixel. Other pixel designs are also well know and could be used in array 102. The pixel 110 contains a pinned photodiode photosensor 112, transfer gate 114, a floating diffusion region FD to collect charge transferred from the photosensor 112, a reset transistor 116, row select transistor 120 and a source follower output transistor 118.
The reset transistor 116 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa-pix. A reset control signal RST is used to activate the reset transistor 116, which resets the floating diffusion region FD to the array pixel supply voltage Vaa-pix level, as is known in the art. The source follower transistor 118 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa-pix and the row select transistor 120. The source follower transistor 118 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 120 is controllable by a row select signal SEL for selectively connecting the source follower transistor 118 and its output voltage signal Vout to a column line 122 of the pixel array 102.
In operation, the pixels 110 of each row in the array 102 are all turned on at the same time by a row select line and the pixels 110 of each column are selectively output onto a column line 122. A plurality of row and column lines are provided for the entire array 102. The row select lines which control pixel transistors within a row are selectively activated by row decoder 130 and driver circuitry 132 in response to an applied row address. Column select lines are selectively activated in response to an applied column address by column circuitry that includes column decoder 134. Thus, row and column addresses are provided for each pixel 110. The CMOS imager 100 is operated by an imager control and image processing circuit 150, which controls the row and column circuitry for selecting the appropriate row and column lines for pixel readout.
Each column is connected to sampling capacitors and switches in the S/H circuitry 136. A pixel reset signal Vrst and a pixel image signal Vsig for selected pixels are sampled and held by the S/H circuitry 136. A differential signal (e.g., Vrst−Vsig) is produced for each readout pixel by the differential amplifier 138 (AMP), which applies a gain to the signal received from the S/H circuitry 136. The differential signal is digitized by an analog-to-digital converter 140 (ADC). The analog-to-digital converter 140 supplies the digitized pixel signals to the imager control and image processing circuit 150, which among other things, forms a digital image output. The imager also contains biasing/voltage reference circuitry 144.
Ideally, digital images created through the use of CMOS and other solid state imagers are exact duplications of the imaged scene projected upon the imager arrays. However, pixel saturation, analog-to-digital conversion saturation, exposure, and gain setting limitations and bit width processing limitations in an imager can limit the dynamic range of a digital image of the scene.
Each of the pixels 110 of pixel array 102 has a characteristic dynamic range. Dynamic range refers to the range of incident light that can be accommodated by a pixel in a single image frame. It is desirable to have pixels with a high dynamic range to image scenes that generate high dynamic range incident signals, such as indoor rooms with windows to the outside, outdoor scenes with mixed shadows and bright sunshine, and night-time scenes combining artificial lighting and shadows.
The dynamic range for a pixel is commonly defined as the ratio of its largest non-saturating signal to the standard deviation of its noise under dark conditions. The dynamic range is limited on an upper end by the charge saturation level of the pixel photosensor and on a lower end by noise imposed limitations and/or quantization limits of the analog-to-digital converter used to produce a digital signal from analog pixel signals. When the dynamic range of a pixel is too small to accommodate the variations in light intensities of the imaged scene, e.g. by having a low saturation level, image distortion occurs.
There are many techniques designed to achieve high dynamic range image outputs from a pixel. Some approaches which have been employed include signal companding, multiple image signal storage, and image signal controlled reset. Companding involves compressing and subsequently expanding a signal to increase the dynamic range, but suffers from drawbacks such as requiring a non-linear pixel output that hampers subsequent processing and causes increased pixel fixed pattern noise (FPN), a dip in the signal to noise ratio (SNR) at the knee point, and low contrast at high brightness. Structures providing multiple signal storage and signal controlled reset may not be practical because they require an increase in die area due to required additional column circuitry.
Another approach to increase dynamic range is to use multiple image captures with different integration times. Dual image capture with a pixel array, for example, is relatively simple to implement, but suffers from an signal-to-noise-ratio dip at the knee point of the collected charge relative to the output signal. A multiple image capture approach that requires more than two image captures is difficult to implement and requires high speed, non-destructive, readout along with on-chip memory and additional column circuitry.
Other approaches to increasing dynamic range rely on pixels that have a variable response to adapt to higher illumination levels (e.g., linear response at lower illumination levels and, for example, logarithmic response at higher illumination). Some techniques rely on variable bias conditions to remove a percentage of any accumulated charge at higher illumination levels. Yet other techniques use variable exposure times. Pixels that use variable response circuit techniques like logarithmic pixels or that use variable bias conditions to spill off excess charge typically suffer from pixel-to-pixel response variation. This variation occurs due to the difficulty in achieving high precision transistor device matching in the pixels throughout a pixel array. Methods that use variable exposure time must tradeoff spatial resolution for rows of pixels with different exposure times. This tradeoff is undesirable. In addition, there are other techniques that add multiple transistors to the pixel circuits. The use of additional transistors in a pixel for improving dynamic range lowers the photosensor “fill factor” and does not allow for small-sized pixels.
Another technique suggested for pixel high dynamic range operation includes providing multiple integration times by using a barrier overflow technique, which means that electrons are caused to overflow a barrier threshold of a transistor coupled to the pixel photosensor, thereby allowing more charge to accumulate in the photosensor. Currently known barrier overflow techniques used to achieve multiple integration times for high dynamic range operation, however, have disadvantages, including variations in the barrier threshold from pixel to pixel due to fabrication process differences for pixel transistors in an array, making it difficult to build a high dynamic range imager with high performance, especially for color imaging. Variations in the barrier thresholds from pixel to pixel cause errors in a pixel signal linearization process which assumes the same barrier threshold for all pixels of an array.
Accordingly, there exists a need for a technique for achieving multiple integration times to achieve a high dynamic range operation, while mitigating problems with transistor fabrication differences from pixel to pixel. It is further desirable to provide a high performance color imager for high dynamic range applications.